70 lines
1001 B
VHDL
70 lines
1001 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop is
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port(
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Q : out std_logic;
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Clk : in std_logic;
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D : in std_logic
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);
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end flipflop;
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architecture Behavioral of flipflop is
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begin
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process(Clk)
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begin
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if(rising_edge(Clk)) then
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Q <= D;
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end if;
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end process;
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end Behavioral;
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architecture rtl of debouncer is
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component flipflop is
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port (
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Q : out std_logic;
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Clk :in std_logic;
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D :in std_logic
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);
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end component flipflop;
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signal s_q1, s_q2, s_q3, s_q4, s_d4, s_and, s_or : std_logic;
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begin
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s_d4 <= s_or and not (enable or reset);
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s_or <= s_q4 or s_and;
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s_and <= s_q2 and not s_q3;
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dff1 : flipflop port map (
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Q => s_q1,
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Clk => clock,
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D => button
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);
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dff2 : flipflop port map (
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Q => s_q2,
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Clk => clock,
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D => s_q1
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);
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dff3 : flipflop port map (
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Q => s_q3,
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Clk => clock,
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D => s_q2
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);
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dff4 : flipflop port map (
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Q => s_q4,
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Clk => clock,
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D => s_d4
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);
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button_o <= s_q4;
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end architecture rtl;
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