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13
bat-entity.vhd
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13
bat-entity.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bat is
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port(button_up : in std_logic;
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button_down : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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bat_o : out std_logic_vector(8 downto 0));
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end entity bat;
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30
bat-rtl.vhd
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30
bat-rtl.vhd
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architecture rtl of bat is
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signal s_bat : std_logic_vector(8 downto 0);
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begin
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bat_o <= s_bat;
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move : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_bat <= "000111000";
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elsif (enable = '1') then
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if(button_up = '1' and button_down = '0' and s_bat /= "111000000") then
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s_bat <= s_bat(7 downto 0) & '0';
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end if;
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if(button_down = '1' and button_up = '0' and s_bat /= "000000111") then
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s_bat <= '0' & s_bat(8 downto 1);
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end if;
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end if;
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end if;
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end process;
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end architecture rtl;
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12
collision-entity.vhd
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12
collision-entity.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity collision is
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port(x_dir : in std_logic;
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y_dir : in std_logic;
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x_pos : in std_logic_vector(11 downto 0);
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y_pos : in std_logic_vector(8 downto 0);
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bat_pos : in std_logic_vector(8 downto 0);
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change : out std_logic);
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end entity collision;
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13
collision-rtl.vhd
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13
collision-rtl.vhd
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architecture rtl of collision is
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signal s_x_pos_1 : std_logic_vector(11 downto 0);
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signal s_y_pos_1 : std_logic_vector(8 downto 0);
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begin
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s_x_pos_1 <= x_pos(10 downto 0) & '0' when (x_dir = '1' and x_pos(11) = '0') or (x_pos(0) = '1' and x_dir='0') else '0' & x_pos(11 downto 1);
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s_y_pos_1 <= y_pos(7 downto 0) & '0' when (y_dir = '1' and y_pos(8) = '0') or (y_pos(0) = '1' and y_dir='0') else '0' & y_pos(8 downto 1);
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change <= '1' when (s_x_pos_1 = "010000000000") and (bat_pos or s_y_pos_1) = bat_pos else '0';
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end architecture rtl;
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11
debouncer-entity.vhd
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11
debouncer-entity.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity debouncer is
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port(button : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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button_o : out std_logic);
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end entity debouncer;
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69
debouncer-rtl.vhd
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69
debouncer-rtl.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity flipflop is
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port(
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Q : out std_logic;
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Clk : in std_logic;
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D : in std_logic
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);
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end flipflop;
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architecture Behavioral of flipflop is
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begin
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process(Clk)
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begin
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if(rising_edge(Clk)) then
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Q <= D;
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end if;
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end process;
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end Behavioral;
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architecture rtl of debouncer is
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component flipflop is
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port (
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Q : out std_logic;
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Clk :in std_logic;
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D :in std_logic
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);
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end component flipflop;
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signal s_q1, s_q2, s_q3, s_q4, s_d4, s_and, s_or : std_logic;
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begin
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s_d4 <= s_or and not (enable or reset);
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s_or <= s_q4 or s_and;
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s_and <= s_q2 and not s_q3;
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dff1 : flipflop port map (
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Q => s_q1,
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Clk => clock,
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D => button
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);
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dff2 : flipflop port map (
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Q => s_q2,
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Clk => clock,
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D => s_q1
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);
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dff3 : flipflop port map (
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Q => s_q3,
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Clk => clock,
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D => s_q2
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);
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dff4 : flipflop port map (
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Q => s_q4,
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Clk => clock,
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D => s_d4
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);
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button_o <= s_q4;
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end architecture rtl;
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11
direction-entity.vhd
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11
direction-entity.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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entity direction is
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port(change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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dir : out std_logic);
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end entity direction;
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24
direction-rtl.vhd
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24
direction-rtl.vhd
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architecture rtl of direction is
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signal s_dir: std_logic;
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begin
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dir <= s_dir;
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fsm : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_dir <= '1';
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elsif (s_dir = '1' and change = '1' and enable = '1') then
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s_dir <= '0';
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elsif (s_dir = '0' and change = '1' and enable = '1') then
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s_dir <= '1';
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else
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s_dir <= s_dir;
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end if;
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end if;
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end process;
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end architecture rtl;
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13
movement-entity.vhd
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13
movement-entity.vhd
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@ -0,0 +1,13 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity movement is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port( dir : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0));
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end entity movement;
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25
movement-rtl.vhd
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25
movement-rtl.vhd
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architecture rtl of movement is
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signal s_pos: std_logic_vector( WIDTH-1 DOWNTO 0);
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begin
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pos <= s_pos;
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fsm : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_pos <= INIT;
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else
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if (dir = '1' and enable = '1' and s_pos(WIDTH-1) /= '1' ) then
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s_pos <= (s_pos(WIDTH-2 DOWNTO 0) & '0');
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elsif (dir = '0' and enable = '1' and s_pos(0) /= '1') then
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s_pos <= ( '0' & s_pos(WIDTH-1 DOWNTO 1));
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end if;
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end if;
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end if;
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end process;
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end architecture rtl;
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14
movement_full-entity.vhd
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14
movement_full-entity.vhd
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@ -0,0 +1,14 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity movement_full is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port(ext_change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0);
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dir_o : out std_logic);
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end entity movement_full;
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54
movement_full-rtl.vhd
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54
movement_full-rtl.vhd
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architecture rtl of movement_full is
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component movement is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port ( dir : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0));
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end component movement;
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component direction is
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port (change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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dir : out std_logic);
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end component direction;
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signal s_and1, s_and2, s_or, s_dir: std_logic;
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signal s_pos: std_logic_vector(WIDTH - 1 downto 0);
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begin
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s_or <= ext_change or s_and1 or s_and2;
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s_and1 <= s_dir and s_pos(WIDTH-2);
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s_and2 <= not s_dir and s_pos(1);
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dir_o <= s_dir;
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pos <= s_pos;
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M: movement
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generic map (
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WIDTH => WIDTH,
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INIT => INIT
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)
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port map (
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dir => s_dir,
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enable => enable,
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reset => reset,
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clock => clock,
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pos => s_pos
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);
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D: direction
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port map (
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change => s_or,
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enable => enable,
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reset => reset,
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clock => clock,
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dir => s_dir
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);
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end architecture rtl;
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13
pong-entity.vhd
Normal file
13
pong-entity.vhd
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@ -0,0 +1,13 @@
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library ieee;
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use ieee.std_logic_1164.all;
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entity pong is
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port(n_button_up : in std_logic;
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n_button_down : in std_logic;
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n_reset : in std_logic;
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clock : in std_logic;
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playfield : out std_logic_vector(107 downto 0);
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0));
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end entity pong;
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164
pong-rtl.vhd
Normal file
164
pong-rtl.vhd
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@ -0,0 +1,164 @@
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architecture rtl of pong is
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component clock_divider is
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port ( clock : IN std_logic;
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reset : IN std_logic;
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enable : OUT std_logic
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);
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end component clock_divider;
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component bat is
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port(button_up : in std_logic;
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button_down : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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bat_o : out std_logic_vector(8 downto 0));
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end component bat;
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component collision is
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port(x_dir : in std_logic;
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y_dir : in std_logic;
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x_pos : in std_logic_vector(11 downto 0);
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y_pos : in std_logic_vector(8 downto 0);
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bat_pos : in std_logic_vector(8 downto 0);
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change : out std_logic);
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end component collision;
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component debouncer is
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port(button : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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button_o : out std_logic);
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end component debouncer;
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component movement_full is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port(ext_change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0);
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dir_o : out std_logic);
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end component movement_full;
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component score is
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port(x_pos : in std_logic_vector(11 downto 0);
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0);
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over : out std_logic);
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end component score;
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signal s_reset : std_logic;
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signal s_enable : std_logic;
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signal s_button_up : std_logic;
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signal s_button_down : std_logic;
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signal s_bat_pos : std_logic_vector(8 downto 0);
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signal s_bat_pos_x : std_logic_vector(11 downto 0) := "010000000000";
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signal s_collision : std_logic;
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signal s_x_pos : std_logic_vector(11 downto 0);
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signal s_y_pos : std_logic_vector(8 downto 0);
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signal s_x_dir : std_logic;
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signal s_y_dir : std_logic;
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signal s_over : std_logic;
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begin
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display : FOR y IN 8 DOWNTO 0 GENERATE
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oneline : FOR x IN 11 DOWNTO 0 GENERATE
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playfield(y*12+x) <= (s_y_pos(y) AND s_x_pos(x)) OR ( s_bat_pos_x(x) and s_bat_pos(y));
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END GENERATE oneline;
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END GENERATE display;
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s_reset <= not n_reset;
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cD : clock_divider
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port map (
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clock => clock,
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reset => s_reset,
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enable => s_enable
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);
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uBD : debouncer
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port map (
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button => n_button_up,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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button_o => s_button_up
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);
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dBD : debouncer
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port map (
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button => n_button_down,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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button_o => s_button_down
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);
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b : bat
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port map (
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button_up => s_button_up,
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button_down => s_button_down,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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bat_o => s_bat_pos
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);
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x_pos : movement_full
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generic map (
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WIDTH => 12,
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INIT => "000000100000"
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)
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port map (
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ext_change => s_collision,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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pos => s_x_pos,
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dir_o => s_x_dir
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);
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y_pos : movement_full
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generic map (
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WIDTH => 9,
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INIT => "000010000"
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)
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port map (
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ext_change => '0',
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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pos => s_y_pos,
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dir_o => s_y_dir
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);
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scoreCounter : score
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port map(
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x_pos => s_x_pos,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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user => user,
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sys => sys,
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over => s_over
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);
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collisionDetector : collision
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port map (
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x_dir => s_x_dir,
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y_dir => s_y_dir,
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x_pos => s_x_pos,
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y_pos => s_y_pos,
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bat_pos => s_bat_pos,
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change => s_collision
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);
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end architecture rtl;
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14
score-entity.vhd
Normal file
14
score-entity.vhd
Normal file
@ -0,0 +1,14 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity score is
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port(x_pos : in std_logic_vector(11 downto 0);
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
|
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0);
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over : out std_logic);
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end entity score;
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64
score-rtl.vhd
Normal file
64
score-rtl.vhd
Normal file
@ -0,0 +1,64 @@
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architecture rtl of score is
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type displayArray is array(9 downto 0) of std_logic_vector(7 downto 0);
|
||||
|
||||
signal display : displayArray;
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||||
|
||||
signal USER_SCORE : integer range 0 to 9;
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signal SYS_SCORE : integer range 0 to 9;
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||||
signal next_user_score : integer range 0 to 9;
|
||||
signal next_sys_score : integer range 0 to 9;
|
||||
signal s_over : std_logic;
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||||
signal s_next_over : std_logic;
|
||||
|
||||
begin
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||||
|
||||
display(0) <= "11111100";
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||||
display(1) <= "01100000";
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||||
display(2) <= "11011010";
|
||||
display(3) <= "11110010";
|
||||
display(4) <= "01100110";
|
||||
display(5) <= "10110110";
|
||||
display(6) <= "10111110";
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||||
display(7) <= "11100000";
|
||||
display(8) <= "11111110";
|
||||
display(9) <= "11110110";
|
||||
|
||||
next_user_score <= USER_SCORE + 1 when x_pos(0) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else USER_SCORE;
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||||
next_sys_score <= SYS_SCORE + 1 when x_pos(11) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else SYS_SCORE;
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||||
s_next_over <= '1' when (next_user_score = 9 or next_sys_score = 9) else '0';
|
||||
|
||||
user <= display(USER_SCORE);
|
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sys <= display(SYS_SCORE);
|
||||
over <= s_over;
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||||
|
||||
scoreProcess : process(clock)
|
||||
begin
|
||||
|
||||
if rising_edge(clock) then
|
||||
|
||||
if (reset = '1') then
|
||||
USER_SCORE<= 0;
|
||||
SYS_SCORE <= 0;
|
||||
elsif (enable = '1') then
|
||||
USER_SCORE <= next_user_score;
|
||||
SYS_SCORE <= next_sys_score;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
overProcess : process(clock)
|
||||
begin
|
||||
|
||||
if rising_edge(clock) then
|
||||
if (reset = '1') then
|
||||
s_over <= '0';
|
||||
elsif (enable = '1') then
|
||||
s_over <= s_next_over;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture rtl;
|
||||
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