26 lines
520 B
VHDL
26 lines
520 B
VHDL
architecture rtl of movement is
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signal s_pos: std_logic_vector( WIDTH-1 DOWNTO 0);
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begin
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pos <= s_pos;
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fsm : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_pos <= INIT;
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else
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if (dir = '1' and enable = '1' and s_pos(WIDTH-1) /= '1' ) then
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s_pos <= (s_pos(WIDTH-2 DOWNTO 0) & '0');
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elsif (dir = '0' and enable = '1' and s_pos(0) /= '1') then
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s_pos <= ( '0' & s_pos(WIDTH-1 DOWNTO 1));
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end if;
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end if;
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end if;
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end process;
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end architecture rtl;
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