31 lines
552 B
VHDL
31 lines
552 B
VHDL
architecture rtl of bat is
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signal s_bat : std_logic_vector(8 downto 0);
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begin
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bat_o <= s_bat;
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move : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_bat <= "000111000";
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elsif (enable = '1') then
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if(button_up = '1' and button_down = '0' and s_bat /= "111000000") then
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s_bat <= s_bat(7 downto 0) & '0';
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end if;
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if(button_down = '1' and button_up = '0' and s_bat /= "000000111") then
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s_bat <= '0' & s_bat(8 downto 1);
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end if;
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end if;
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end if;
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end process;
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end architecture rtl;
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