65 lines
1.5 KiB
VHDL
65 lines
1.5 KiB
VHDL
architecture rtl of score is
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type displayArray is array(9 downto 0) of std_logic_vector(7 downto 0);
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signal display : displayArray;
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signal USER_SCORE : integer range 0 to 9;
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signal SYS_SCORE : integer range 0 to 9;
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signal next_user_score : integer range 0 to 9;
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signal next_sys_score : integer range 0 to 9;
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signal s_over : std_logic;
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signal s_next_over : std_logic;
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begin
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display(0) <= "11111100";
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display(1) <= "01100000";
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display(2) <= "11011010";
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display(3) <= "11110010";
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display(4) <= "01100110";
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display(5) <= "10110110";
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display(6) <= "10111110";
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display(7) <= "11100000";
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display(8) <= "11111110";
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display(9) <= "11110110";
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next_user_score <= USER_SCORE + 1 when x_pos(0) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else USER_SCORE;
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next_sys_score <= SYS_SCORE + 1 when x_pos(11) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else SYS_SCORE;
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s_next_over <= '1' when (next_user_score = 9 or next_sys_score = 9) else '0';
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user <= display(USER_SCORE);
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sys <= display(SYS_SCORE);
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over <= s_over;
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scoreProcess : process(clock)
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begin
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if rising_edge(clock) then
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if (reset = '1') then
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USER_SCORE<= 0;
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SYS_SCORE <= 0;
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elsif (enable = '1') then
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USER_SCORE <= next_user_score;
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SYS_SCORE <= next_sys_score;
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end if;
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end if;
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end process;
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overProcess : process(clock)
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begin
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if rising_edge(clock) then
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if (reset = '1') then
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s_over <= '0';
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elsif (enable = '1') then
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s_over <= s_next_over;
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end if;
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end if;
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end process;
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end architecture rtl;
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