vhdl_pong/direction-entity.vhd
2019-10-01 01:26:10 +02:00

12 lines
229 B
VHDL

library ieee;
use ieee.std_logic_1164.all;
entity direction is
port(change : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
dir : out std_logic);
end entity direction;