12 lines
229 B
VHDL
12 lines
229 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity direction is
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port(change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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dir : out std_logic);
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end entity direction;
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