25 lines
435 B
VHDL
25 lines
435 B
VHDL
architecture rtl of direction is
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signal s_dir: std_logic;
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begin
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dir <= s_dir;
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fsm : process(clock)
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begin
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if rising_edge(clock) then
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if(reset = '1') then
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s_dir <= '1';
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elsif (s_dir = '1' and change = '1' and enable = '1') then
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s_dir <= '0';
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elsif (s_dir = '0' and change = '1' and enable = '1') then
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s_dir <= '1';
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else
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s_dir <= s_dir;
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end if;
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end if;
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end process;
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end architecture rtl;
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