15 lines
382 B
VHDL
15 lines
382 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity movement_full is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port(ext_change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0);
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dir_o : out std_logic);
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end entity movement_full;
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