14 lines
406 B
VHDL
14 lines
406 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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entity pong is
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port(n_button_up : in std_logic;
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n_button_down : in std_logic;
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n_reset : in std_logic;
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clock : in std_logic;
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playfield : out std_logic_vector(107 downto 0);
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0));
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end entity pong;
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