165 lines
3.5 KiB
VHDL
165 lines
3.5 KiB
VHDL
architecture rtl of pong is
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component clock_divider is
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port ( clock : IN std_logic;
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reset : IN std_logic;
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enable : OUT std_logic
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);
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end component clock_divider;
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component bat is
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port(button_up : in std_logic;
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button_down : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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bat_o : out std_logic_vector(8 downto 0));
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end component bat;
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component collision is
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port(x_dir : in std_logic;
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y_dir : in std_logic;
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x_pos : in std_logic_vector(11 downto 0);
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y_pos : in std_logic_vector(8 downto 0);
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bat_pos : in std_logic_vector(8 downto 0);
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change : out std_logic);
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end component collision;
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component debouncer is
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port(button : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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button_o : out std_logic);
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end component debouncer;
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component movement_full is
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generic(WIDTH : natural := 9;
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INIT : std_logic_vector);
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port(ext_change : in std_logic;
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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pos : out std_logic_vector(WIDTH - 1 downto 0);
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dir_o : out std_logic);
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end component movement_full;
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component score is
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port(x_pos : in std_logic_vector(11 downto 0);
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0);
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over : out std_logic);
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end component score;
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signal s_reset : std_logic;
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signal s_enable : std_logic;
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signal s_button_up : std_logic;
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signal s_button_down : std_logic;
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signal s_bat_pos : std_logic_vector(8 downto 0);
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signal s_bat_pos_x : std_logic_vector(11 downto 0) := "010000000000";
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signal s_collision : std_logic;
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signal s_x_pos : std_logic_vector(11 downto 0);
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signal s_y_pos : std_logic_vector(8 downto 0);
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signal s_x_dir : std_logic;
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signal s_y_dir : std_logic;
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signal s_over : std_logic;
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begin
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display : FOR y IN 8 DOWNTO 0 GENERATE
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oneline : FOR x IN 11 DOWNTO 0 GENERATE
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playfield(y*12+x) <= (s_y_pos(y) AND s_x_pos(x)) OR ( s_bat_pos_x(x) and s_bat_pos(y));
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END GENERATE oneline;
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END GENERATE display;
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s_reset <= not n_reset;
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cD : clock_divider
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port map (
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clock => clock,
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reset => s_reset,
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enable => s_enable
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);
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uBD : debouncer
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port map (
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button => n_button_up,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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button_o => s_button_up
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);
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dBD : debouncer
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port map (
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button => n_button_down,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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button_o => s_button_down
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);
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b : bat
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port map (
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button_up => s_button_up,
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button_down => s_button_down,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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bat_o => s_bat_pos
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);
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x_pos : movement_full
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generic map (
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WIDTH => 12,
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INIT => "000000100000"
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)
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port map (
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ext_change => s_collision,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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pos => s_x_pos,
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dir_o => s_x_dir
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);
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y_pos : movement_full
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generic map (
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WIDTH => 9,
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INIT => "000010000"
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)
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port map (
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ext_change => '0',
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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pos => s_y_pos,
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dir_o => s_y_dir
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);
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scoreCounter : score
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port map(
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x_pos => s_x_pos,
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enable => s_enable,
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reset => s_reset,
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clock => clock,
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user => user,
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sys => sys,
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over => s_over
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);
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collisionDetector : collision
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port map (
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x_dir => s_x_dir,
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y_dir => s_y_dir,
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x_pos => s_x_pos,
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y_pos => s_y_pos,
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bat_pos => s_bat_pos,
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change => s_collision
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);
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end architecture rtl;
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