15 lines
363 B
VHDL
15 lines
363 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity score is
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port(x_pos : in std_logic_vector(11 downto 0);
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enable : in std_logic;
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reset : in std_logic;
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clock : in std_logic;
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user : out std_logic_vector(7 downto 0);
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sys : out std_logic_vector(7 downto 0);
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over : out std_logic);
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end entity score;
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