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charlesbvll 2019-10-01 01:26:10 +02:00 committed by GitHub
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bat is
port(button_up : in std_logic;
button_down : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
bat_o : out std_logic_vector(8 downto 0));
end entity bat;

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architecture rtl of bat is
signal s_bat : std_logic_vector(8 downto 0);
begin
bat_o <= s_bat;
move : process(clock)
begin
if rising_edge(clock) then
if(reset = '1') then
s_bat <= "000111000";
elsif (enable = '1') then
if(button_up = '1' and button_down = '0' and s_bat /= "111000000") then
s_bat <= s_bat(7 downto 0) & '0';
end if;
if(button_down = '1' and button_up = '0' and s_bat /= "000000111") then
s_bat <= '0' & s_bat(8 downto 1);
end if;
end if;
end if;
end process;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity collision is
port(x_dir : in std_logic;
y_dir : in std_logic;
x_pos : in std_logic_vector(11 downto 0);
y_pos : in std_logic_vector(8 downto 0);
bat_pos : in std_logic_vector(8 downto 0);
change : out std_logic);
end entity collision;

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architecture rtl of collision is
signal s_x_pos_1 : std_logic_vector(11 downto 0);
signal s_y_pos_1 : std_logic_vector(8 downto 0);
begin
s_x_pos_1 <= x_pos(10 downto 0) & '0' when (x_dir = '1' and x_pos(11) = '0') or (x_pos(0) = '1' and x_dir='0') else '0' & x_pos(11 downto 1);
s_y_pos_1 <= y_pos(7 downto 0) & '0' when (y_dir = '1' and y_pos(8) = '0') or (y_pos(0) = '1' and y_dir='0') else '0' & y_pos(8 downto 1);
change <= '1' when (s_x_pos_1 = "010000000000") and (bat_pos or s_y_pos_1) = bat_pos else '0';
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity debouncer is
port(button : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
button_o : out std_logic);
end entity debouncer;

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library ieee;
use ieee.std_logic_1164.all;
entity flipflop is
port(
Q : out std_logic;
Clk : in std_logic;
D : in std_logic
);
end flipflop;
architecture Behavioral of flipflop is
begin
process(Clk)
begin
if(rising_edge(Clk)) then
Q <= D;
end if;
end process;
end Behavioral;
architecture rtl of debouncer is
component flipflop is
port (
Q : out std_logic;
Clk :in std_logic;
D :in std_logic
);
end component flipflop;
signal s_q1, s_q2, s_q3, s_q4, s_d4, s_and, s_or : std_logic;
begin
s_d4 <= s_or and not (enable or reset);
s_or <= s_q4 or s_and;
s_and <= s_q2 and not s_q3;
dff1 : flipflop port map (
Q => s_q1,
Clk => clock,
D => button
);
dff2 : flipflop port map (
Q => s_q2,
Clk => clock,
D => s_q1
);
dff3 : flipflop port map (
Q => s_q3,
Clk => clock,
D => s_q2
);
dff4 : flipflop port map (
Q => s_q4,
Clk => clock,
D => s_d4
);
button_o <= s_q4;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity direction is
port(change : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
dir : out std_logic);
end entity direction;

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architecture rtl of direction is
signal s_dir: std_logic;
begin
dir <= s_dir;
fsm : process(clock)
begin
if rising_edge(clock) then
if(reset = '1') then
s_dir <= '1';
elsif (s_dir = '1' and change = '1' and enable = '1') then
s_dir <= '0';
elsif (s_dir = '0' and change = '1' and enable = '1') then
s_dir <= '1';
else
s_dir <= s_dir;
end if;
end if;
end process;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity movement is
generic(WIDTH : natural := 9;
INIT : std_logic_vector);
port( dir : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
pos : out std_logic_vector(WIDTH - 1 downto 0));
end entity movement;

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architecture rtl of movement is
signal s_pos: std_logic_vector( WIDTH-1 DOWNTO 0);
begin
pos <= s_pos;
fsm : process(clock)
begin
if rising_edge(clock) then
if(reset = '1') then
s_pos <= INIT;
else
if (dir = '1' and enable = '1' and s_pos(WIDTH-1) /= '1' ) then
s_pos <= (s_pos(WIDTH-2 DOWNTO 0) & '0');
elsif (dir = '0' and enable = '1' and s_pos(0) /= '1') then
s_pos <= ( '0' & s_pos(WIDTH-1 DOWNTO 1));
end if;
end if;
end if;
end process;
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity movement_full is
generic(WIDTH : natural := 9;
INIT : std_logic_vector);
port(ext_change : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
pos : out std_logic_vector(WIDTH - 1 downto 0);
dir_o : out std_logic);
end entity movement_full;

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architecture rtl of movement_full is
component movement is
generic(WIDTH : natural := 9;
INIT : std_logic_vector);
port ( dir : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
pos : out std_logic_vector(WIDTH - 1 downto 0));
end component movement;
component direction is
port (change : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
dir : out std_logic);
end component direction;
signal s_and1, s_and2, s_or, s_dir: std_logic;
signal s_pos: std_logic_vector(WIDTH - 1 downto 0);
begin
s_or <= ext_change or s_and1 or s_and2;
s_and1 <= s_dir and s_pos(WIDTH-2);
s_and2 <= not s_dir and s_pos(1);
dir_o <= s_dir;
pos <= s_pos;
M: movement
generic map (
WIDTH => WIDTH,
INIT => INIT
)
port map (
dir => s_dir,
enable => enable,
reset => reset,
clock => clock,
pos => s_pos
);
D: direction
port map (
change => s_or,
enable => enable,
reset => reset,
clock => clock,
dir => s_dir
);
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
entity pong is
port(n_button_up : in std_logic;
n_button_down : in std_logic;
n_reset : in std_logic;
clock : in std_logic;
playfield : out std_logic_vector(107 downto 0);
user : out std_logic_vector(7 downto 0);
sys : out std_logic_vector(7 downto 0));
end entity pong;

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architecture rtl of pong is
component clock_divider is
port ( clock : IN std_logic;
reset : IN std_logic;
enable : OUT std_logic
);
end component clock_divider;
component bat is
port(button_up : in std_logic;
button_down : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
bat_o : out std_logic_vector(8 downto 0));
end component bat;
component collision is
port(x_dir : in std_logic;
y_dir : in std_logic;
x_pos : in std_logic_vector(11 downto 0);
y_pos : in std_logic_vector(8 downto 0);
bat_pos : in std_logic_vector(8 downto 0);
change : out std_logic);
end component collision;
component debouncer is
port(button : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
button_o : out std_logic);
end component debouncer;
component movement_full is
generic(WIDTH : natural := 9;
INIT : std_logic_vector);
port(ext_change : in std_logic;
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
pos : out std_logic_vector(WIDTH - 1 downto 0);
dir_o : out std_logic);
end component movement_full;
component score is
port(x_pos : in std_logic_vector(11 downto 0);
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
user : out std_logic_vector(7 downto 0);
sys : out std_logic_vector(7 downto 0);
over : out std_logic);
end component score;
signal s_reset : std_logic;
signal s_enable : std_logic;
signal s_button_up : std_logic;
signal s_button_down : std_logic;
signal s_bat_pos : std_logic_vector(8 downto 0);
signal s_bat_pos_x : std_logic_vector(11 downto 0) := "010000000000";
signal s_collision : std_logic;
signal s_x_pos : std_logic_vector(11 downto 0);
signal s_y_pos : std_logic_vector(8 downto 0);
signal s_x_dir : std_logic;
signal s_y_dir : std_logic;
signal s_over : std_logic;
begin
display : FOR y IN 8 DOWNTO 0 GENERATE
oneline : FOR x IN 11 DOWNTO 0 GENERATE
playfield(y*12+x) <= (s_y_pos(y) AND s_x_pos(x)) OR ( s_bat_pos_x(x) and s_bat_pos(y));
END GENERATE oneline;
END GENERATE display;
s_reset <= not n_reset;
cD : clock_divider
port map (
clock => clock,
reset => s_reset,
enable => s_enable
);
uBD : debouncer
port map (
button => n_button_up,
enable => s_enable,
reset => s_reset,
clock => clock,
button_o => s_button_up
);
dBD : debouncer
port map (
button => n_button_down,
enable => s_enable,
reset => s_reset,
clock => clock,
button_o => s_button_down
);
b : bat
port map (
button_up => s_button_up,
button_down => s_button_down,
enable => s_enable,
reset => s_reset,
clock => clock,
bat_o => s_bat_pos
);
x_pos : movement_full
generic map (
WIDTH => 12,
INIT => "000000100000"
)
port map (
ext_change => s_collision,
enable => s_enable,
reset => s_reset,
clock => clock,
pos => s_x_pos,
dir_o => s_x_dir
);
y_pos : movement_full
generic map (
WIDTH => 9,
INIT => "000010000"
)
port map (
ext_change => '0',
enable => s_enable,
reset => s_reset,
clock => clock,
pos => s_y_pos,
dir_o => s_y_dir
);
scoreCounter : score
port map(
x_pos => s_x_pos,
enable => s_enable,
reset => s_reset,
clock => clock,
user => user,
sys => sys,
over => s_over
);
collisionDetector : collision
port map (
x_dir => s_x_dir,
y_dir => s_y_dir,
x_pos => s_x_pos,
y_pos => s_y_pos,
bat_pos => s_bat_pos,
change => s_collision
);
end architecture rtl;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity score is
port(x_pos : in std_logic_vector(11 downto 0);
enable : in std_logic;
reset : in std_logic;
clock : in std_logic;
user : out std_logic_vector(7 downto 0);
sys : out std_logic_vector(7 downto 0);
over : out std_logic);
end entity score;

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architecture rtl of score is
type displayArray is array(9 downto 0) of std_logic_vector(7 downto 0);
signal display : displayArray;
signal USER_SCORE : integer range 0 to 9;
signal SYS_SCORE : integer range 0 to 9;
signal next_user_score : integer range 0 to 9;
signal next_sys_score : integer range 0 to 9;
signal s_over : std_logic;
signal s_next_over : std_logic;
begin
display(0) <= "11111100";
display(1) <= "01100000";
display(2) <= "11011010";
display(3) <= "11110010";
display(4) <= "01100110";
display(5) <= "10110110";
display(6) <= "10111110";
display(7) <= "11100000";
display(8) <= "11111110";
display(9) <= "11110110";
next_user_score <= USER_SCORE + 1 when x_pos(0) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else USER_SCORE;
next_sys_score <= SYS_SCORE + 1 when x_pos(11) = '1' and not(USER_SCORE = 9 or SYS_SCORE = 9) else SYS_SCORE;
s_next_over <= '1' when (next_user_score = 9 or next_sys_score = 9) else '0';
user <= display(USER_SCORE);
sys <= display(SYS_SCORE);
over <= s_over;
scoreProcess : process(clock)
begin
if rising_edge(clock) then
if (reset = '1') then
USER_SCORE<= 0;
SYS_SCORE <= 0;
elsif (enable = '1') then
USER_SCORE <= next_user_score;
SYS_SCORE <= next_sys_score;
end if;
end if;
end process;
overProcess : process(clock)
begin
if rising_edge(clock) then
if (reset = '1') then
s_over <= '0';
elsif (enable = '1') then
s_over <= s_next_over;
end if;
end if;
end process;
end architecture rtl;